Milan, Italy
Originally published: 20/11/2017
PJDLS (Padded Jittering Data Link byte Stuffed) v2.0
Invented by Giovanni Blu Mitolo,
released into the public domain

Related implementation: /strategies/AnalogSampling/
Compliant versions: PJON v10.0 and following

- Frame separation obtained with SFSP v2.0

PJDLS v2.0

PJDLS (Padded Jittering Data Link byte Stuffed) is a simplex or half-duplex data link layer, that can be easily software emulated, enabling one or many to many communication in both master-slave and multi-master configuration, optimized for use cases where high quality synchronization cannot be achieved. Frame separation is obtained with the use of SFSP v1.0. It has been engineered to have limited minimum requirements, and to be efficiently executed on limited microcontrollers with poor clock accuracy. No additional hardware is required to apply PJDLS, and, being implemented in c++, in less than 350 lines of code, it is easily portable to many different architectures.

Basic concepts

  • Define a synchronization pad initializer to identify a byte
  • Use synchronization pad's falling edge to achieve byte level synchronization
  • Detect interference or absence of communication at byte level
  • Frame separation obtained with SFSP v1.0
  • Support collision avoidance
  • Support 1 byte synchronous response to frame

Byte transmission

Each byte is prepended with a synchronization pad and transmission occurs LSB-first. The first bit is a longer than standard logic 1 followed by a standard logic 0. The reception method is based on finding a logic 1 as long as the first padding bit within a certain threshold, synchronizing to its falling edge and checking if it is followed by a logic 0. If this pattern is detected, reception starts, if not, interference, synchronization loss or simply absence of communication is detected at byte level.

 __________ ___________________________
| SyncPad  | Byte                      |
|______    |___       ___     _____    |
|  |   |   |   |     |   |   |     |   |
|  | 1 | 0 | 1 | 0 0 | 1 | 0 | 1 1 | 0 |
Minimum acceptable HIGH padding bit duration

Padding bits add a certain overhead but are reducing the need of precise timing because synchronization is renewed every byte. The first padding bit duration is the synchronization timeframe the receiver has to receive a byte. If the length of the first padding bit is less than the minimum acceptable duration, the received signal is considered interference.

Synchronous response

A frame transmission can be optionally followed by a synchronous response by its recipient. This feature is available for both master-slave and multi-master. In multi-master configuration the maximum acceptable acknowledgement overall response time must be less than the initial channel analysis duration before frame transmission.

Transmission                                    Response
 _______  ______  ______  _____                   _____
|  149  ||  H   ||  I   || 234 | LATENCY         |  6  |
|_______||______||______||_____|                 |_____|

In master-slave configuration the maximum time dedicated to potential acknowledgement reception it is defined by the use case constraints like maximum packet length and latency or physical distance between devices.

Communication modes

The proposed communication modes are the result of years of testing and optimization for light pulses communication and have been selected to be easily supported also by limited microcontrollers.

MODE Bit timing Sync bit timing Pad-bit ratio Speed
1 750 1050 1.4 128B/s - 1024Bb
2 572 728 1.2727 170B/s - 1361Bb
3 188 428 2.2765 471B/s - 3773Bb
4 128 290 2.2656 639B/s - 5547Bb
5 56 128 2.2857 1582B/s - 12658Bb

Binary timing durations are expressed in microseconds.

This document is automatically generated from the github repository. If you have noticed an error or an inconsistency, please report it opening an issue here